Two (2) duplicate compact discs, each containing two files named xe2x80x9cApp_a.txtxe2x80x9d and xe2x80x9cApp_b.txtxe2x80x9d, corresponding respectively to Appendix A and Appendix B, are incorporated herein by reference.
The present invention relates generally to generating hardware description language code, and more particularly to systems and methods for generating boundary scan configuration files and VERILOG netlists.
To reduce the cost of device component and system testing, integrated circuits (ICs) and printed circuit boards (PCBs) often have built-in-self-test (BIST) features incorporated into the components. To standardize the test methodology and port architecture, the Joint Test Access Group (JTAG) created the Institute for Electrical and Electronic Engineers (IEEE) standard 1149.1, also known as IEEE Standard Test Access Port and Boundary Scan Architecture. IEEE standard 1149.1 defines a four to five wire serial interface, an instruction set, and a test protocol. The test port of an 1149.1 standard device allows for serial loading of test instructions and data into the device, and for the test results to be serially read out.
FIG. 1 illustrates an IEEE 1149.1 compatible device 10. A JTAG compatible device has a four pin test port (TCK=Test Clock 20, TMS=Test Mode Select 30, TDI=Test Data In 40, and TDO=Test Data Out 50), an optional 5th reset pin (TRST=Test Reset 60), a Test Access Port (TAP) Controller 70, an Instruction Register (IR) 80, a Bypass register (BPR) 90, a Boundary Scan Register (BSR) 100, and an optional user Data Register (DR) 110. Each input and output pin of a 1149.1 compatible device has a Boundary Scan Cell (BSC) 120 and 122, which contains a set of control registers and gates (not shown). The boundary scan register or BSR 100 is made up of serially connected BSCs 120 and 122 as illustrated in FIG. 1. Serially connected BSCs 120 and 122 are also called the scan path. The boundary scan chain is the path from TDI 40, through the BSR 100, to TDO 50.
The TAP controller 70 is a state machine that, in conjunction with the IR 80, controls operations associated with the BSR 100. The TAP controller 70 is clocked by TCK 20, and its state is controlled by TMS 30. TDI 40 and TDO 50 receive the data input and output signals for the boundary scan chain. Working in conjunction with the TAP controller 70, the IR 80 is loaded with instructions that determine the particular test to be performed.
There are three required test instructions defined by IEEE Std 1149.1, BYPASS, SAMPLE/PRELOAD, and EXTEST. The BYPASS instruction keeps the IC in a functional mode, and enables serial data to pass through the IC from TDI 40 through the BPR 90 to TDO 50 without affecting the operation of the rest of the device. The SAMPLE/PRELOAD instruction keeps the IC in its functional mode, and selects BSR 100 to be connected between TDI 40 and TDO 50. Executing SAMPLE/PRELOAD instruction allows the BSR 100 to be accessed to sample the data entering and leaving the IC or to preload test data into the BSR 100. The EXTEST instruction places the IC into a test mode, and selects the BSR 100 to be connected between TDI 40 and TDO 50. Executing EXTEST loads the BSCs 122 associated with output pins 130 with the test patterns to be input into downstream devices, and prepares the input boundary cells 120 to capture the input data.
A hardware description language (HDL) is a code for describing a circuit. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication. The two most popular HDLs are VHSIC Hardware Description Language (VHDL) and VERILOG. VHDL was developed by the U.S. Department of Defense and is an open standard. VERILOG, also called Open VERILOG International (OVI), is an industry standard developed by a private entity, and is now an open standard referred to as IEEE Standard 1364. A file written in VERILOG code that describes a JTAG compliant device is called a VERILOG netlist. VHDL is an HDL defined by IEEE standard 1076.1. Boundary Scan Description Language (BSDL) is a subset of VHDL, and provides a standard machine- and human-readable data format for describing how an IEEE Std 1149.1 boundary-scan architecture is implemented and operates in a device.
Commercial products exist that generate the boundary scan description language (BSDL) files and VERILOG netlists. To generate a BSDL file, such products generally require input files with many parameters and must be composed using exact syntax. For instance, a BSDL description for a device consists of several elements. These elements include entity descriptions, a generic parameter, a logical port description, use statement(s), a component conformance statement, pin mapping(s), a scan port identification, an instruction register description, an optional register description, a register access description, and a boundary register description. Some products require an input file containing a register transfer language (RTL) representation of the device, such as a VERILOG or VHDL description. Other products require an input file with device parameters specified by a manufacturer defined syntax. To generate the files in the proper format requires learning the various programming languages or manufacturer defined syntax. When the files are created, even small errors in syntax can result in time-consuming debugging of the input files. Consequently, generating the input files that describe the boundary scan architecture is time-consuming and requires a skilled programmer. Thus, the current systems and methods of generating VERILOG netlists and BSC files are labor intensive, prone to inaccuracies, and slow. Systems and methods of improving the speed, accuracy, and simplicity of generating HDL files are needed.
The present invention includes systems, methods, scripts, and signals useful for generating hardware description language (HDL) files that describe circuits. To generate an HDL file, a user may access a hardware description code generation host, typically via the Internet, and upload information about the circuit. The hardware description code generation host may in turn generate an HDL file from the uploaded information, referred to as the input parameters, which the user uploads to the host. The hardware description code generation host utilizes scripts, which are generally software programs, to generate the files from the input parameters. The input parameters contain information about the ports of the device, which are utilized in generating the files. Information about the format for entering the input parameters may be displayed to the user on the same webpage as the input form, or through a separate webpage easily accessible by clicking on hyperlinks to other webpages. Moreover, the user may customize the input format to suit his particular needs. After the hardware description language files are generated, the user may save or download the files from the host.
The present invention has several advantages over the prior art. First, the present invention eliminates the labor intensive processes of learning the HDL syntax and debugging the HDL files to correct syntax errors. Instead of having to learn an HDL-like VERILOG or BSDL to generate HDL files, the user will input simple port descriptions and the script will generate the files. Second, the details of the input format for entering the input parameters may be displayed on the input form, which will eliminate the need to memorize the input format, or the cumbersome process of referring to a manual to learn formatting details. The present invention even allows a user to customize the input format to his own needs. Third, since VERILOG netlists and BSDL files differ significantly, a user typically generates each separately. The present invention allows both the VERILOG netlist and the BSDL files to be generated from one file of input parameters, again, eliminating a labor intensive process. Thus, the systems and methods of the present invention improve the speed, accuracy, and simplicity of hardware description code generation, and overcome the limitations and shortcomings of the prior art.
In accordance with one aspect of the present invention an Internet hardware description code generation system is provided. The Internet hardware description code generation system includes a hardware description code generation host. The hardware description code generation host is adapted to generate one or more hardware description language files in response to one or more input parameters uploaded thereto. The one or more input parameters may describe a circuit, and these parameters may include one or more port descriptions. The circuits described by the input parameters may include circuits that have at least one device that complies substantially with IEEE standard 1149.1, circuits that have at least one boundary scan cell, at least one test access port controller, at least one bypass register, and at least one instruction register, and circuits that have at least one boundary scan chain.
The one or more input parameters may be uploaded to the hardware description code generation host via the Internet. An input format for inputting the one or more input parameters may be displayed to a user substantially simultaneously as the user inputs the input parameters. The input format for inputting the one or more input parameters may be pre-defined or customized by a user. The input form may be an HTML form. The hardware description code generation host may utilize at least one script for customizing an input form for inputting the one or more input parameters.
The hardware description code generation host may be a computer. The hardware description code generation host may utilize at least one script for generating the one or more hardware description language files. At least one of the one or more hardware description language files generated may be a VERILOG netlist or a boundary scan configuration file, and may be generated in VHSIC Hardware Description Language, a Boundary Scan Description Language or in VERILOG. The present invention also includes hardware description language files generated by the Internet hardware description code generation systems described herein.
In accordance with one aspect of the present invention an Internet hardware description code generation method is provided. The Internet hardware description code generation method includes interfacing a user and a hardware description code generation host, receiving one or more input parameters describing a circuit from the user, and generating one or more hardware description language files from the one or more input parameters received from the user. The one or more input parameters may include one or more port descriptions. The circuits described by the input parameters may include circuits that have at least one device that substantially complies with IEEE standard 1149.1, circuits that have at least one boundary scan cell, at least one test access port controller, at least one bypass register, and at least one instruction register, and circuits that have at least one boundary scan chain. The user and the hardware description code generation host may be interfaced via the Internet. The user may download the one or more hardware description language files from the hardware description code generation host, and/or the one or more hardware description language may be stored on data storage media.
The hardware description code generation host may be a computer. The hardware description code generation host may utilize at least one script for generating the one or more hardware description language files. At least one of the one or more hardware description language files generated may be a VERILOG netlist or a boundary scan configuration file. The hardware description code generation host may include data storage media for storing the hardware description language files. The hardware description code generation host may utilize at least one script for generating the one or more hardware description language files.
An input format for inputting the one or more input parameters may be displayed to a user substantially simultaneously as the user inputs the input parameters. The input format for inputting the one or more input parameters may be pre-defined or customized by a user. The input form may be in an HTML format. The hardware description code generation host may utilize at least one script for customizing an input form for inputting the one or more input parameters. The user may use a computer to link to the hardware description code generation host via the Internet to upload the one or more input parameters to the hardware description code generation host. The present invention also includes hardware description language files generated by the Internet hardware description code generation methods described herein.
In another aspect of the present invention, an electronic signal adapted to be transmitted between at least two computers is provided. The electronic signal includes one or more input parameters describing a circuit. The one or more input parameters may be received by a hardware description code generation host, and the hardware description code generation host may generate one or more hardware description language files from the one or more input parameters. The electronic signal may be stored in electronic memory, such as random access memory.
In yet another aspect of the present invention, an electronic signal adapted to be transmitted between at least two computers is provided. The electronic signal includes one or more hardware description language files describing a circuit. The one or more hardware description language files may be generated from one or more input parameters that are received by a hardware description code generation host. The electronic signal may be stored in electronic memory, such as random access memory.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain aspects and embodiments of the invention. These aspects and embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages, and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.